1. Field of the Invention
The present invention relates to a semiconductor manufacturing method, and more particularly to a method for forming an interconnect that serves as a contact between regions of an electronic device.
2. Description of the Background
During the semiconductor fabrication process, multiple conductive layers such as metal or polysilicon layers are often deposited on a semiconductor substrate. Conductive layers are sometimes separated from each other by an insulating dielectric layer, such as silicon dioxide. These conductive layers are often selectively connected or "wired" together in order to allow for conduction of electricity in a desired pattern.
FIGS. 1A-FIG. 1J illustrate a method of making a connection between different conductive layers of a semiconductor substrate.
In FIG. 1A, a dielectric oxide layer 104 is shown deposited on top of a patterned local interconnect ("LI") 102. LI 102 may be a metal (e.g. titanium tungsten (TiW)) or a polysilicon gate member or other conductive material, such as a silicide, or doped polysilicon.
In FIG. 1B, the dielectric oxide layer 104 is polished.
In FIG. 1C, a contact or a via 106 through the dielectric oxide 104 is created by a suitable technique such as with a mask and etching, ending at the patterned LI 102.
As illustrated in FIG. 1D, the next step is to deposit an adhesive layer 108 over the dielectric oxide 104 and into the opening 106, without completely filling the opening 106. An adhesive layer helps an overlying conductive layer adhere to dielectric oxide layer 104 and may itself be formed of a conductive material such as titanium.
A conductive material, such as tungsten (W) 110, is then deposited as a conductive layer on top of the adhesive layer 108 until the opening 106 is filled as illustrated in FIG. 1E. There may be a small depression in the conductive material layer 110 (not shown) over the opening 106.
In FIG. 1F, an etch back is performed on the conductive 110 layer but the etch is stopped at the adhesive layer 108. Thus, a portion of the surface of the conductive layer is exposed as shown in FIG. 1F.
As illustrated in FIGS. 1G and 1H, a layer of a photoresist 114 is deposited covering adhesive layer 108 and onto the exposed portion of conductor 110. A mask 112 is used to pattern a local interconnect ("LI") 116 by etching the adhesive layer 108. The LI 116 has been formed by adhesive layer 108 and stripping photoresist 114.
FIG. 1I illustrates a dielectric oxide layer 118 which has been deposited over dielectric oxide 104 and a contact formed such as by a mask and etch of dielectric oxide 118. The result is an opening 120 formed in the dielectric oxide layer 118.
The previous steps are repeated as shown in FIG. 1J, when an adhesive layer 122 such as titanium is deposited over dielectric oxide layer 118 and a blanket layer of conductive material 124 is deposited on top of the adhesive layer 122. The conductive material 124 is then etched back so that only a portion of the conductive material 124 is shown in the opening. The etch of the conductive material 124 stops at the adhesive layer 122. In this way, LI 102 is connected to a LI 116 and to adhesive layer 122.
This method has several disadvantages. The contact surface of opening 120 in FIG. 1I is often compromised due to insufficient cleaning of the bottom of the contact opening 120. In addition, when LI 116 is made of a material having a low melting point (e.g. titanium), it is difficult to heat treat the bottom of the contact opening 120 to remove contaminants without causing LI 116 to reflow. Difficulties in getting adhesive layer 122 to the bottom of the opening 120 can also occur, especially when an opening has a high aspect ratio. This method is labor-intensive (i.e., two conductive material depositions and two etch-backs), thus increasing the possibility of error or contamination from the increased complexity of processing.
Thus, a need exists for a relatively simple process for making reliable connections between conductive material layers and/or local interconnects of a semiconductor substrate.